1. Field of the Invention
The present invention relates to the field of data processing. More particularly, the invention relates to a timing control circuit for controlling a signal timing in an associated circuit.
2. Description of the Prior Art
In a data processing system, it can be useful to control a signal timing within a circuit of the data processing system. For example, it may not be easy to predict in advance which timings should be used since the ideal signal timing may vary from system to system depending on the configuration of circuit elements used in the system, manufacturing process variations and other characteristics of the system. Also, it may be desirable to provide reference timings that can varied in accordance with application requirements. For example, a more aggressive scheduling with a shorter delay between reference timings can increase performance, while for a safety-critical application the timings can be relaxed in order to reduce the likelihood of errors. Hence, a tunable timing control circuit for controlling reference timings for an associated circuit may be desirable.
In a memory, for example, reference timings can be controlled using a dummy loop circuit. The dummy loop circuit has a dummy cell that mimics a real memory cell of the memory array. When a dummy word line of the dummy cell is asserted, then a dummy sense amplifier reads a dummy value from the dummy cell over a dummy bit line. The timing with which the dummy value is returned from the dummy cell is correlated with the timing of similar operations within the memory array and so can be used to trigger events in the memory array, such as the triggering of a sense amplifier or the resetting of a word line.
To vary the reference timing provided by the dummy loop circuit, the dummy cell may be provided with a number of switchable control cells which can be switched on and off individually in order to increase or decrease the current flow through the dummy loop. When a greater number of control cells are switched into the path of the dummy loop, more current flows through the dummy loop, causing the dummy loop to return its data value more quickly and hence triggering the generation of the reference timing at an earlier time.
However, providing such variable timing control requires a large amount of circuit area. Typically, a decoder is provided to convert a control value, which specifies the number of control cells that are to be switched on in the dummy loop path, into signals for switching each individual control cell. For example, if there are 16 control cells, then this requires a 4:16 decoder which converts a 4-bit binary value into 16 1-bit signals for switching the individual cells. The 4:16 decoder requires many transistors (typically about 136 transistors). This area overhead is expensive and contributes greatly to the total circuit area of the memory. Hence, it is desirable to reduce the area overhead associated with the timing control.